Semiconductor chips are comprised of a series of integrated circuits and devices which include transistors. Transistors are of two general types, namely bipolar and field effect transistors (alternately termed FET). One common type of FET transistor are MOS transistors which are formed of complementary p-type and n-type conductivity material.
Complementary MOS (CMOS) is a MOS circuit formed with both n-channel and p-channel devices, namely a n-type transistor (nMOS) and a p-type transistor (pMOS). The nMOS transistors have their source and drain regions formed of n-type material in a p-type substrate or p-well, while pMOS transistors have their source and drain regions formed of a p-type material in an n-type substrate or n-well. CMOS allows more powerful circuit operation than either n-channel or p-channel circuits alone. This factor, combined with lower power consumption and increased speed, has made CMOS the favorite technology for the manufacture of microprocessors and memory devices.
Memory circuitry typically comprises an array of memory cells, each being comprised of a transistor and an associated capacitor. The operating voltage (V.sub.cc) of such transistors is typically 5 volts. N-channel transistors operating at 5 volts typically require a lighter doped n-implant region adjacent their active n-regions for reliable operation. Such regions are typically formed adjacent the pair of active n-regions inwardly therebetween by formation of oxide spacers on the edges of the transistor gate. Such regions are commonly referred to as "lightly doped drains" (LDD). However, such regions are positioned inwardly adjacent both of the source and drains of a FET transistor, rather than just the drain region as the terminology implies. One drawback to LDD implants is that they typically require added space on the wafer than non-LDD transistors due to the extra space required for the implants between the active n-regions.
As transistor feature sizes have become smaller due to higher densities, the DRAM memory cell n-channel transistors are expected to require internal V.sub.cc voltages of approximately 3.3 volts. At such operation voltages, LDD structures may not be desirable or necessary. However, some peripheral n-channel devices outside of the DRAM memory cell will need to be designed to handle, at burn-in testing, operating voltages of 5.0 volts or higher, which may require LDD and its associated spacer technology.